Micro Magic, Inc.'s mission is to dramatically reduce the time and cost required to produce high-performance SoC designs.
Micro Magic was founded in January of 1995. The founders worked together at SUN Microsystems. While at SUN they worked on several projects including a 900ps 16Kbyte cache SRAM, the SPARC V9 architecture definition, and led a team to develop a 300MHz SPARC Microprocessor. The rest of the core design team consists of senior designers from companies like HP, SGI, and DEC. Most have Ph.D.'s from Stanford, Berkeley, and MIT and average almost 20 years of industry experience
DPC is the tool used by designers needing high performance chips. They want the performance of full custom design, but with a much shorter design cycle. Datapaths designed with DPC are 3X (three times) faster and 40% smaller than synthesis and place and route. At the same time, it takes 10X (ten times) less effort than full custom design
MAX is much more than a layout tool; it is an intelligent IC layout environment. MAX includes interactive cross-probing between layout and schematic. Automatic generation of layout from schematics (a feature of MAX-LS) provides true schematic-driven layout. And, with real-time interactive DRC, MAX shows you any DRC errors right on the layout! No memorizing design rules or counting grids.
The MegaCell Compiler (MCC) makes building all types of regular structures such as SRAMs, CAMs, DRAMs, Register Files, FIFOs, ROMs, PLAs, and even pad rings, fast and easy. The MegaCell Compiler is so fast that any size repetitive structure can be built in the comparable time it takes to load the data from the disk. Mere seconds for even multi-Mbit SRAMs.
SUE is not just another schematic capture tool. SUE is a quantum leap in technology that gives the designer the ability to enter, visualize, and control large, complex chip designs. It is a complete design environment in which to capture all levels and types of design information