Library Technologies, Inc.

Library Technologies, Inc. develops and markets design and analysis tools for integrated circuit design. The tools and products are integrated together. They interface to popular chip designs flows. SolutionWare product line covers characterization and modeling requirements for standard cells, IO and memories including functional verification and design library generation.

Product Name: CCSTEST: Library Verification and Correlation
Product Category: Design Verification

CcsTest is a suite of tools which are used for verifying the accuracy of of an existing Liberty library. They are part of SolutionWare. They can be automatically executed by makelib ccstests
which carries out all intermediate steps for all the corners and library cells. The tool suite was originally designed to test Current Source Models like CCS and ECSM.

Product Name: CellOpt™
Product Category: IC Physical Design Tools - ASIC and IC Design

CellOpt is a dynamic circuit level power/timing optimizer designed to minimize the power dissipation of standard build blocks like logic gates and sequential elements, with optional timing constraints, by properly sizing the devices used in the circuit. After all, energy is consumed by these components, and how well they are designed and how well they fit to their particular use on the chip is of paramount importance.

Product Name: ChipTimer
Product Category: Cell & Block Characterization - ASIC and IC Design

ChipTimer is a design optimization and timing closure tool for high performance designs. It is well known that algorithms and architecture are the most important element of performance, but implementation has a lot of leeway impacting performance.

Product Name: PowerTeam
Product Category: Design Libraries - ASIC and IC Design

PowerTeam is a dynamic power simulator. It is integrated with Verilog and provides power simulation and analysis capabilities to Verilog on top of Verilog's functional and timing simulation capabilities. Interface to Verilog is through PLI. Verilog-XL and VCS are supported. In addition to PLI interface, power simulation requires a power library which describes different power dissipation modes of the library elements. Various power dissipation parameters are also contained in this library.

Product Name: SolutionWare
Product Category: Design Libraries - ASIC and IC Design

Solutionware library generation tools offer the most comprehensive set of tools for characterization and model generation. They are optimized for speed and efficiency. They can cover even non-standard cells like one-hot muxes, semi-synchronous flops, synchronizers, clock gating cells, dynamic flops and dual edge flops, and even cells which mux between flip-flop and latch behavior. Characterization time for a flip-flop could be as small as 2 minutes for 7x7 tables generated without interpolation.

Product Name: UnBlock and RcBack
Product Category: Design Libraries - ASIC and IC Design

UnBlock is a library generator for Structured Custom Layout Blocks. These blocks are usually handcrafted, don't use an ASIC library, and usually take advantage of circuit and layout techniques which are normally avoided in standard cell designs. The main problem with these blocks is the difficulty of functional and timing verification. Transistor level timing and functional simulators are the only available tools designers can rely on.

Product Name: YieldOpt: Process Variation Analysis
Product Category: Design Verification

YieldOpt addresses the issue of variation of process and its impact on the timing aspects of the chip design. Process variation is becoming more and more significant with each new process generation. A single sigma parameter was thought to be sufficient to summarize the variation of previous generations of processes, the variation for new generations may require tens of new independent random variables to characterize the variations on the same die, same wafer, and different lots. Coupled with supply voltage sensitivity, and new temperature effects, it becomes quite a challenge to find proper process and environmental conditions for design and timing analysis.

19959 Lanark Lane
Saratoga, CA 95070
United States
Phone: 408-741-1214
Fax: 408-867-2753
Contact us
Featured Video
Latest Blog Posts
Bob Smith, Executive DirectorBridging the Frontier
by Bob Smith, Executive Director
Combatting Software Piracy
Stefano LorenziniArteris IP Blog
by Stefano Lorenzini
Scalability – A Looming Problem in Safety Analysis
Anupam BakshiAgnisys Automation Review
by Anupam Bakshi
Automating UVM-Based IP and SoC Functional Verification
FPGA DESIGN for L3Harris at Burlington,, Canada
Upcoming Events
SEMI MEMS & Imaging Sensors Summit at World Trade Center WTC; 5-7 Place Robert Schuman Grenoble France - Sep 6 - 7, 2022
SEMICON Taiwan 2022 a at TaiNEX 1 Taipei Taiwan - Sep 14 - 16, 2022
MIPI DevCon 2022 - Virtual Event at United States - Sep 20 - 21, 2022
2022 International Test Conference at Disney Land Hotel Anaheim CA - Sep 26 - 29, 2022

© 2022 Internet Business Systems, Inc.
670 Aberdeen Way, Milpitas, CA 95035
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise