Simutest was founded in 1987 to provide innovative automation solutions
for semiconductor designers and production test developers.
Our first product to improve productivity and lower
manufacturing costs was directed at Vector Translation between circuit
simulation and ATE. The tool was delivered to the market in 1991.
To provide a migration path between a variety of production
ATE systems, our second product for Tester Conversion was released in
1995 and later followed by the Rule Analyzer in 1999 in order to help
designers identify ATE-related issues early in their device release
Simutest announces the ATE-Ready. The ATE-Ready is a pattern conversion
and verification software that accepts functional test vectors in the
VCD/EVCD or tabular format as inputs and generates cyclized test vectors
in the industry standard test vector formats such as WGL or STIL. The
ATE-Ready software has built-in capability to analyze the input test
vectors against the tester capabilities and restrictions to ensure
that the generated WGL or STIL files are compatible with the target ATE.
In addition, the ATE-Ready software also provides capability to
playback the cyclized vectors in the Verilog simulation to validate that
the generated WGL or STIL files meet the design intent.
Product Name: Rule Analyzer
- System Level Design (ESL)
Rule Analyzer is a test vector analysis product that can be used to analyze simulation or ATPG generated test vectors against a set of user defined rules. The Rule Analyzer product can be used in either design or test environment to identify compatibility of design test vectors against a particular test methodology or target ATE capabilities and restrictions. Additionally, the Rule Analyzer may also be used to detect the compliance of test vectors against the device datasheet timing specifications.
The SiliconDebug is a software product that maps the ATE captured data
log of silicon failures into the design environment. For graphical
viewing of silicon failures, the ATE-debug software generates a VCD
file. User has flexibility to select the signals and time intervals for
display. E.g. the VCD file may contain waveforms for all device pins or
waveforms for only the failing pins or waveforms for the selected pins
during the fail time interval(s). Additionally, the compare module of
the SiliconDebug software compares and reports the differences between
the source simulation patterns with silicon captured patterns or ATE
stored patterns in a text report file.
Simcompare is a test vector comparison program that can be used by the design and test engineers to:
- Compare Simulation / ATPG test vectors with ATE test vectors.
- Compare best and worst case or pre/post layout Simulations.
- Compare test vectors between two testers for the same design
Semiconductor production test environment often needs to migrate test programs from one test system to another for capacity and/or obsolescence reasons. The T2T
is a conversion program that converts existing test programs from one test system into the test language of the target test system.
Product Name: TP-Builder
Design for Test
- ASIC and IC Design
The TP-Builder is a custom software framework for automating the process of development of complete test programs for the production test systems for a set of structured digital devices. The TP-builder framework integrates the vector conversion with the parametric DC tests thus creating standardized production test programs in a matter of minutes instead of days.
Product Name: Verifier
- System Level Design (ESL)
The Verifier vector translator is a comprehensive and full featured automatic test program development tool. It continues to be the latest in the test automation technology and efficiently meets the challenges associated with converting simulation / ATPG test vectors into various tester formats. The Verifier addresses both time to market as well as improved design to manufacturing productivity.