Averant is a startup electronic design automation (EDA) company
focusing on verification of complex ICs and digital intellectual
property (IP). The continuing growth in design complexity has caused a
functional gap between what can be built and what can be verified
before production. Finding mistakes after production can cost hundreds
of millions of dollars, as seen with the Intel Pentium and the Toshiba
floppy disk controller bugs. Averant closes the functional verification
gap by delivering a new static verification technology that guarantees
blocks used in design are functionally correct before production.
SolidAC™ is a
program that automatically checks a circuit for a number of common design
problems. Reading only the design source, and with very little input from the
user, AutoChecks tracks down such problems as clock domain crossing problems,
and a host of other problems that cause a design to function improperly.
Solidify™ Static functional verification is a unique
form of analysis applied to RTL design descriptions. The strength of this
analysis is that it is exhaustive by nature, and quickly uncovers hidden design
flaws and corner cases.
AMBA compliance in a snap. Built upon formal technology, SolidPC employs a pre-defined set of technology rules to verify compliance with the AMBA protocol specification. SolidPC has an easy, flow-oriented interface, and requires no vectors to run. Leveraging the Solidify core engine, the tool efficiently executes a series of exhaustive proofs, automatically generating testbenches for rules that fail.
SolidSEC verifies that two versions of a circuit are
functionally equivalent after sequential optimizations are performed on one circuit.
Examples of such optimizations are clock gating and retiming which occur during
power reduction optimizations.
Confidence with timing analysis. SolidTC is a timing constraint verifier that checks the validity of False-paths and Multi-cycle paths declared in an SDC file. Built upon the Solidify engine, it uses formal techniques to quickly and exhaustively verify correctness of these timing exceptions.