Atrenta's SpyGlass Predictive Analyzer® significantly improves design efficiency for the world's leading semiconductor and consumer electronics companies. Patented solutions provide early design insight into the demanding performance, power and area requirements of the complex system on chips (SoCs) fueling today's consumer electronics revolution. More than two hundred fifty companies and thousands of design engineers worldwide rely on SpyGlass to reduce risk and cost before traditional EDA tools are deployed. And with the addition of BugScope™, verification efficiency is also enhanced, allowing engineers and managers to find the fastest and least expensive path to silicon for complex SoCs.
Atrenta’s SpyGlass, GenSys® and BugScope™ product families of SoC Realization tools enhance the entire system development cycle -- from architectural planning to physical implementation.
Product Name: GenSys Assembly
- Structured/Platform ASICs
Architecture Generation & Programmed Handoff
The need for higher design efficiencies in all semiconductor product development has led to an increased focus on IP reuse and platform-based design techniques. The ability to perform comprehensive architectural planning/optimization and communicate the goals of the design to downstream team members with clear specifications and no ambiguity represent substantial competitive differentiation. The goal of these activities is always the same leverage a design investment across multiple similar socket opportunities, and win those sockets through cost and time-to-market advantages. The GenSys® Assembly product provides an environment to realize these goals.
The GenSys Assembly solution has been developed over more than three years with a leading semiconductor company servicing consumer markets. The goal of this work has been to reduce front-end development effort for SoC platforms and derivative designs by more than an order of magnitude, while also dramatically reducing the level of human error in assembly. To accomplish these goals, Atrenta has developed a product that moves beyond early market concepts of platform-based design as the starting point for a new
Early design analysis for logic designers
Using advanced static and dynamic analysis, the SpyGlass solution pinpoints structural, coding and consistency problems at RTL. In addition, the solution offers the industy's most comprehensive solution for analysis of RTL structures, clocks and, resets and clock domain crossings (CDC). It provides formal analysis of RTL for FSM correctness, bus contention, dead code and other critical functional issues, without requiring testbench or assertions. It traces problems to their source, helps users resolve issues before they creep into downstream design implementation. The SpyGlass solution also helps address electrical rules (ERC) in the design.
SpyGlass-CDC is the industry’s most comprehensive, practical, and powerful Clock Domain Crossing solution. Spyglass-CDC automatically identifies and formally verifies all synchronization schemes that you throw at it.
Specify Constraints Early, Validate Continuously & Automate Handoff
Creating and ensuring correct and consistent constraints, at all levels of the design hierarchy and throughout the design cycle, is a vital and increasingly challenging task. The difficulties can include: writing new constraints; managing thousands of lines of legacy constraints; managing thousands of timing exceptions across the design flow; unwanted iterations due to changing constraints; and erroneous constraints resulting in redesigns and even re-spins.
The SpyGlass® Constraints solution provides a big productivity boost to IC design efforts by automating the creation, validation and management of constraints. The SpyGlass Constraints solution generates new constraints where needed and verifies that existing constraints are correct and consistent across all phases of development: pre-synthesis, pre-layout and post-layout.
Design for Test at RTL
The SpyGlass® DFT solution has the unique ability to predict ATPG (automatic test pattern generation) test coverage and pinpoint testability issues as the RTL description is developed, even before a gate-level netlist is generated. The SpyGlass DFT solution not only detects testability issues--it can also automatically correct them.
The benefits are substantial. Traditional approaches depend on test engineers to design test clocks and set/reset logic for scan insertion at the gate level, when changes can be difficult, time-consuming and expensive. The SpyGlass DFT solution, by contrast, enables users to tune testability during RTL creation, when the design impact is greatest and the cost of modifications lowest. The SpyGlass DFT solution can significantly shorten development cycles, reduce costs and improve overall testability.
Design for Low Power at RTL
With the SpyGlass® Power solution policies, users can tune their designs for power consumption and efficiency at the register transfer level (RTL). The SpyGlass Power solution provides early information about power consumption at RTL, and provides guidance where power can be reduced. The SpyGlass Power solution not only detects, but can also automatically fix, key power management issues.
The advantages are significant. Traditional approaches address power analysis and optimization at the gate level, making changes difficult and costly and complicating verification. The SpyGlass Power solution, by contrast, enables users to tune power characteristics during RTL creation, when the design impact is greatest and the cost of modifications lowest. It can significantly shorten development cycles, reduce costs and improve the power characteristics of the finished product.