CAST develops, sells, and supports semiconductor IP
(intellectual property) for electronic system designers.
Engineers use our pre-designed and pre-verified IP
Cores and Platform IP products to save development time and add functionality
beyond their areas of expertise.
IP from CAST and similar firms has enabled the design
reuse methodology popular in recent years as a means for handling rising design
complexity and decreasing time to market.
The C32025TX is a single-chip, high performance 16-bit fixed-point digital signal processor core. It implements the same instruction set as the TMS320C25 and provides the same interrupts, serial interface and timer, executing most of instructions in a single clock cycle.
Implements a powerful 32-bit microprocessor is
derived from the Motorola MC68000 microprocessor. The core uses an AMBA-compatible
AHB master interface, making it an ideal processor solution for low-cost,
AHB-based System on Chip (SoC) applications.
Implements a PCI Express endpoint controller that is compliant with PCI Express Base specification 1.0a, including the Transaction, Data Link, and Physical protocol layers.
The scalable and flexible core has a modular architecture and a high-performance, low-latency design. It supports multiple device link widths to better match the bandwidth needs of specific applications—x1 (single lane) and x4 (four lane)—and offers bi-directional data rates from 250MB/s (x1) to 1GB/s (x4).
The DDR2-SDRAM-CTRL core provides a simplified, pipelined and burst-optimized interface to all industry-standard DDR and DDR-II SDRAM devices currently on the market.
The development of increasingly complex microsystems requires the usage of a powerful field bus systems for distributed real-time networks. The CAN protocol has a wide acceptance in the field of serial communication.
A configurable, single-chip, 8-bit microcontroller core that can implement a variety of fast processor variations executing the MCS® 51 instruction set.
The SHA-256 core is a fully compliant implementation of the Message Digest Algorithm SHA-256. It computes a 256-bit message digest for messages of up to (264 – 1) bits.