Anchor Semiconductor, Inc.

Anchor is a pioneer and a worldwide leader in the semiconductor hotspot pattern management and analysis, supplying foundries and design houses with a suite of software solutions to improve IC manufacturing efficiency and chip yield. Under the innovative pattern-centric NanoScope platform, Anchor helps resolving the rapidly increasing challenges of analyzing and managing significant volumes of CD metrology data from IC fab, determining process critical design patterns and optimizes fab processes.

Product Name: Hotspot Pattern Analyzer
Product Category: Design Verification

Hotspot Pattern Analyzer provides powerful solutions for analysis and dispositioning of different types of violations found from design verification to manufacturing process characterization and monitoring. Integrated in NanoScopeā„¢ pattern-centric DFM platform, the hotspot analyzer takes hotspot reports from tools such as OPC verification or layout process sensitivity checking, as well as hotspots detected in manufacturing.

Product Name: NanoScope-DFP
Product Category: Design Verification

NanoScope-DFP is manufacturing-aware design verification tool. It is used at pre-tapeout design stage and complementary to DRC to ensure lithographic-friendly layout. Please contact Anchor specialists for more information.

Product Name: NanoScope-DPL™
Product Category: Design Verification

NanoScope-DPL™ (Defect Pattern Library) is built on Anchor’s pattern-centric NanoScope platform. DPL provides patterning knowledge sharing and reuse, allows users to save patterns from different sources: litho-unfriendly patterns in OPC verification, problematic patterns in mask making, and yield limiting patterns in wafer printing.

Product Name: NanoScope-PRV
Product Category: Design Verification

NanoScope-PRV (PRV) is a market-leading OPC/RET inspection tool. It is a software-based solution which has superior advantages in full-chip accuracy and performance. Together with its unparalleled analysis capability and ease-of-use, PRV provides our customers the fastest ROI and lowest COO (cost of ownership). It is silicon-proven at 0.15um, 0.13um, 0.11um, 90nm and below. It has successfully helped many of our customers around the world to cut down their OPC/RET development cycle time and avoid the costly mask making and wafer fabrication.

3235 Kifer Road
Ste 200
Santa Clara, CA 95051
United States
Phone: 408-986-8969
Fax: 408-986-8999
Contact us


Featured Video
ASIC Hardware Engineer for BAE Systems Intelligence & Security at Arlington, VA
Applications Engineer for intersil at Palm Bay, FL
Design Verification Engineer for intersil at Morrisville, NC
Senior Formal FAE Location OPEN for EDA Careers at San Jose or Anywhere, CA
Senior Electrical Engineer for Allen & Shariff Corporation at Pittsburgh, PA
Upcoming Events
DVCon US 2018 at Double Tree Hotel San Jose CA - Feb 26 - 1, 2018
5th EAI International Conference on Big data and Cloud Computing Challenges at Vandalur, Kelambakkam high road chennai Tamil Nadu India - Mar 8 - 9, 2018
DATE '18: Design, Automation and Test in Europe at International Congress Center Dresden Ostra-Ufer 2 Dresden Germany - Mar 19 - 23, 2018

Internet Business Systems © 2018 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise