Globetech Solutions offers Design Verification and Test solutions optimized for various market segments. By integrating methodologies, planning and IP, we address the complete cycle from specification to validated silicon. By incorporating strong reuse practices into the equation, our solutions target complete platform development across multiple domains and integrated circuits.
The Consumer Electronics Advanced Technology Attachment (CE-ATA) eVC is a complete verification environment capable of verifying CE-ATA compliant Host or Device implementations. Based upon a flexible architecture, the CE-ATA eVC can be instantiated in several different configurations. Use the Device Agent to verify a CE-ATA Host design, the Host Agent to verify a CE-ATA Device design, or a monitor-only configuration to ensure correct operation of a complete-HDL environment.
The JTAG eVC is a complete verification environment based on the IEEE 1149.1-2001 (JTAG) standard. From developing a JTAG TAP controller to designing a complete chip-level test architecture, the JTAG eVC is a valuable tool for identifying design bugs, emphasizing protocol compatibility issues and ensuring smooth interoperability of testability features.
The IEEE 1500 Standard for Embedded Core Test (SECT) is a newly released standard defining the blueprint for building complex test infrastructures within large SoCs. The IEEE 1500 SECT comprises a comprehensive set of guidelines for building such an infrastructure, including the hardware architecture, information model (implemented in the IEEE P1450.6 Core Test Language proposal) and definitions of levels of compliance. The eVC provides automatic vector generation and control signal manipulation while monitoring all test and functional inputs and outputs for correct protocol behavior. The eVC collects coverage metrics on the functionality of the test logic that has been exercised and is used to identify test plan holes and estimate time to closure.
The Infrared Data Association (IrDA®) interface eVC is built around the IrDA Physical Layer Specification which can be used with any IrDA SIR/MIR/FIR device. The eVC provides a powerful verification environment to help designers either implement or integrate an IrDA core in conformance to the IrDA 1.0 SIR and 1.1 MIR/FIR Physical Layer specifications. The eVC’s extended capabilities make it easy to exercise a variety of designs-under-test, providing full metrics for error conditions and functional coverage.
The UART 16x50 eVC is a complete device-level verification environment capable of validating industry standard 16550 through 16950 A-D UART designs. The UART 16x50 eVC is a core or module level eVC. It includes a 16x50 reference model which allows it to fully track activity in the device, providing full functionality coverage including protocol & data interface cross-checking as well as internal register coverage.
The UART eVC is a universal, highly reusable verification component, providing advanced capabilities for generating UART frames, driving and monitoring a UART interface, detecting errors and estimating functional coverage. Adopted by companies worldwide as a building block for reusable verification platforms, it can be integrated in a variety of testing scenarios involving a UART peripheral. It makes no assumptions about internal device architecture; instead, it focuses on driving traffic to the UART interface of the device-under-test (DUT) and observing its behavior. This makes it applicable to virtually any kind of UART DUT.
