Entasys Design, Inc.


Entasys Design Inc. was founded in 2003 to provide EDA solutions for ESL and SOC designers and focused on the development of innovative design automation technology for early stage power and SI aware design to fill the gap between chip implementation and fabrication technologies




Product Name: Optima
Product Category: Design Verification

With semiconductor process technology scaling into nanometer regime, SoC (System-on-Chip) requires more robust power network than ever. However, due to the absence of proper design automation solution, every modification of pad configuration causes extra design iterations or requires excessive power pads increasing chip size. OPTIMA is an optimal pad configuration solution to minimize painful design iterations.

Product Name: Pillar-DP®-Navis
Product Category: IC Physical Design Tools - ASIC and IC Design

There is a rich set of tools available today to support chip design at the register-transfer level. After years of research and development, most of all SoC designers have fairly good understanding on design process based on the RTL of representation.

Product Name: Pillar-DP®-SVP
Product Category: Design Verification

Pillar-DP®-SVP is a comprehensive pre-RTL silicon virtual prototyping (SVP) solution, including micro architecture level power and area estimation, hierarchical floorplanning, package aware IO pad configuration, and automatic power network prototyping. In addition to the SVP capability, the chip level IP integration feature and the constraints interface feature to the integrated chip (IC) implementation help designers achieve the fist-silicon-success and the time-to-market.

Product Name: Pillar-DP®-Ventus
Product Category: IC Physical Design Tools - ASIC and IC Design

At the early stage of SoC design, there are many unknowns and SoC designers have many options available, so this is why making the right choices can be difficult. As behavioral description is not just sufficient to describe the constraints of today's complex SoC design, the innovative methodology is needed to specify and analyze a higher-level of the design representation in early design stage and answer questions about floorplanning, power consumption, area and timing.


422, Hyuandi Venture-Ville, 713, Suseo-Dong
Gangnam-Gu
Seoul 135-539
Korea (North)
Phone: 82-2-2040-7540
Fax: 82-2-2040-7541
Contact us
Url: http://www.entasys.com/



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IPC APEX EXPO 2018 at San Diego Convention Center San Diego CA - Feb 24 - 1, 2018
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5th EAI International Conference on Big data and Cloud Computing Challenges at Vandalur, Kelambakkam high road chennai Tamil Nadu India - Mar 8 - 9, 2018
DownStream: Solutions for Post Processing PCB Designs



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