Aeroflex Gaisler AB

Aeroflex Gaisler provides IP cores and supporting development tools for embedded processors based on the SPARC architecture. The key product is the LEON synthesizable processor model together with a full development environment and a library of IP cores (GRLIB). Our personnel have extended design experience, and have been involved in establishing European standards for ASIC and FPGA development. Aeroflex Gaisler has a long experience in the management of ASIC development projects, and in the design of flight quality microelectronic devices. The company specializes in digital hardware design (ASIC/FPGA) for both commercial and aerospace applications.

Product Name: GRLIB IP
Product Category: Design Verification

The LEON3 processor core is a synthesizable VHDL model of a 32-bit processor complaint with the SPARC V8 architecture. The core is highly configurable and particularly suitable for system-on-a-chip (SOC)desgins.The configurability allows designers to optimize the processor for performance, power consumption, I/O throughput, silicon area and cost. The core is interfaced using the AMBA-2.0 AHB bus, and supports the IP plug& play method provided in the GRLIB IP Library

Product Name: GRMON
Product Category: Debugging - FPGA and PLD Design Tools

GRMON is a debug monitor for LEON processors.

Product Name: GRSPW Spacewire
Product Category: FPGA Synthesis - FPGA and PLD Design Tools

The GRSPW core implements a Spacewire Codec with RMAP support and AMBA host interface. The core implements the Spacewire standard with the protocol identification extension (ECSS-E- 50-12 part 2) and RMAP protocol draft C. Receive and transmit data is autonomously transferred between the Spacewire Codec and the AMBA AHB bus using DMA transfers. Through the use of receive and transmit descriptors, multiple Spacewire packets can be received and transmitted without CPU involvement. The GRSPW control registers are accessed through an APB interface. For critical space applications, a fault-tolerant (FT) version of GRSPW is available with full SEU protection of all RAM blocks.

Product Name: Leon3 Processor
Product Category: HDL Add-In Tools - ASIC and IC Design

The LEON3 is a synthesisable VHDL model of a 32-bit processor compliant with the SPARC V8 architecture. The model is highly configurable, and particularly suitable for system-on-a-chip (SOC) designs. The full source code is available under the GNU GPL license, allowing free and unlimited use for research and education

Product Name: The SPARC Architecture Manual Version 8
Product Category: Documentation Tools - ASIC and IC Design

SPARC was designed as a target for optimizing compilers and easily pipelined hardware implementations. SPARC implementations provide exceptionally high execution rates and short time-to-market development schedules.

Product Name: TSIM ERC32/LEON simulator
Product Category: ASIC Physical Synthesis - ASIC and IC Design

TSIM can be run in stand-alone mode, or connected through a network socket to the GNU gdb debugger. In stand-alone mode, a variety of debugging commands are available to allow manipulation of memory contents and registers, breakpoint/watchpoint insertion and performance measurement. Connected to gdb, TSIM acts as a remote target and supports all gdb debug requests.

Kungsgatan 12
Goteborg SE-411 19
Phone: +46-31-7758650
Fax: +46-31-421-407
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