OneSpin is changing this. With our software tools, an engineer simply states the intention and the software makes sure that these intentions are met, under all conditions. This is achieved by using formal technology and we believe this will fundamentally change the way digital computing devices are designed and verified. Every engineer creating them, every business selling them and ultimately everybody using them will benefit from formal technology.
Product Name: 360 DV-Certify
- Structured/Platform ASICs
For critical IP blocks, 360 DV-Certify offers the highest possible verification quality. Following the GapFreeVerification process, the user develops assertions and achieves 100% functional coverage independent of the chosen functional coverage points - OneSpin's patented GapFreeVerification technology certifies that there is no functionality in the IP apart from the functionality encoded in the assertions, a level of assurance that no other tool can deliver. In other words, any functionality that can contribute to the IO-behavior of the block is actually captured in assertions.
360 DV-Inspect provides the most in-depth, automated static analysis of any tool available, and is an indispensible side-arm for any RTL designer. DV-Inspect is used to rapidly eliminate errors prior to verification or synthesis, delivering a fully automated, simple use-model. The RTL code is targeted using multiple techniques to achieve a rigorous and exhaustive analysis. Formal engines provide more rigorous verification than that available through other techniques, such as standard linting. Assertion synthesis is leveraged to generate comprehensive structural test sets and coverage analysis, further improving quality. A debug tool with simulation trace generator makes understanding issues easy.
OneSpin 360 DV-Verify is the only unified coverage-driven assertion-based verification solution available today. The combination of a fully functional, high-performance formal property analyzer with a unique assertion coverage evaluator eliminates the guesswork from quality assertion generation. DV-Verify is designed to augment existing verification environments, enabling the discovery of elusive bugs hard-to-find in simulation-only environments, while maximizing coverage.
The OneSpin® 360 EC-ASIC Equivalence Checker thoroughly proves, without simulation, that design functionality is maintained through all implementation phases of a design, such as design revisions, synthesis and optimizations, made from RTL to the final netlist – RTL-RTL, RTL-gate and gate-gate – in ASIC/SoC designs. The solution fully automates state and phase mapping via proof-based sequential analysis. A design conditioning component and highly accurate design modeling detect synthesis bugs, synthesis/simulation mismatches and RTL coding bugs that often escape conventional equivalence checking.
Product Name: 360 EC-FPGA
- FPGA and PLD Design Tools
The OneSpin® 360 EC-FPGA solution ensures that advanced FPGA synthesis optimizations – used to achieve competitive functionality, performance, power consumption, and cost targets – do not introduce functional errors. It supports all sequential synthesis optimizations performed in FPGA design flows.
360 EC-FPGA verifies the optimized design 'as is' without gate-level simulation, design modifications or design restrictions – such as disabling synthesis optimizations. It verifies the whole-chip flat netlists, enabling the most aggressive optimizations leading to highly competitive designs.