Silicon Hive technology offers full C-programmability to applications that operate within very constrained area and power budgets, yet require high performance points. Currently, such applications are predominantly implemented using inflexible hardwired logic.
Such highly challenging combinations of requirements are typically found in high-performance digital signal processing for imaging, video, and communications in consumer devices. On the other side of the performance spectrum, however, the same challenges are found in ultra low-power applications, such as medical sensor networks, where compute performance requirements may be modest, but low power dissipation requirements are extreme.
Compute performance of the HiveFlex ISP2xxx is scaled by varying the
quantity of VLIW issue slots [from 4 to 12], as well as the number of
elements per SIMD vector [SIMD factor from 4 to 128]. The table below
indicates the associated performance in GOPs, and the sustained
throughput using two reference applications: the high-quality Primary
ISP (*1) and video mode at 30fps with 3D noise reduction and image
stabilization.
Performance is scaled to build a complete video processing system by
concatenating multiple VP tiles. The video processing chain is
constructed on the multi-tile platform by compiling individual video
processing kernels on the VP tiles.
VLSI area and power will vary with the features of the ISP, as well as
the maximum pixel processing rate supported by the HW system. Multiple
configurations are currently available to support differing pixel
densities and processing rates. The table below indicates the sustained throughput using two reference
applications: the high-quality Primary ISP (*1) and video mode at 30fps
with 3D noise reduction and image stabilization.
Performance is scaled by concatenating multiple SP and VP tiles. The
video processing chain is constructed on the multi-tile platform by
compiling individual video processing kernels on the tiles. The vector
processing (VP) tile instruction set and architecture is optimized for
video (de)coding and pre/post processing applications. The scalar and
stream processing (SP) tile instruction set architecture is enhanced to
support entropy coding. The architecture is completed by accelerators
for well-defined functionalities.
