PERFECTUS Technology, Inc
Developing cutting edge verification framework technologies and design methodologies and automatic test generation techniques created Perfectus Technology, Inc.. By leveraging over several hundred man-years of development effort that this technology represents, Perfectus is well positioned to bring superior design and verification solutions to market very quickly. With corporate headquarters in Santa Clara, CA and design centers in Bangalore, & Bhubaneswar, India, Perfectus brings together a global team with strong expertise in design, verification, backend, board design, firmware and software to deliver high quality product development solutions.
Genie-Ethernet VIP is an Open verification methodology
(OVM) implementation of IEEE Standard 802.3
Genie ONFi Verification IP is based on OVM 2.0 and fully
compliant to ONFi 2.1 Revision specifications. It is a complete
verification suite that helps designers to verify a NAND Flash Device.
The VIP can behave as an ONFi Host and Transfer Command, Address and
Data to NAND Flash Device according to the configuration.
Genie-PCIe is a system verilog implementation of
the PCI Express (PCIE) Standards.
GENIE SSU VIP is compliant to Super Speed USB3.0
specifications . It is a complete verification suite
that helps designer to verify a USB 3.0 based designs
. The VIP can behave as a host ( or a downstream port
entity ) or it can behave as a device (or an upstream
port entity ) based on the configuration of the VIP.
The SAS VIP has a Genie-SAS™ verification engine that wraps around the “Design Under Test” (DUT) to simplify test development and accelerate debug of Serial Attached SCSI protocol based designs. It provides a complete framework to quickly develop self-checking, comprehensive tests for SAS-based initiator, target, or expander devices.
Perfectus has created a many-tiered product offering specifically aimed at delivering Serial ATA controller designs to market faster, with reduced effort and higher quality. These products are designed to solve the problem that absorbs the largest resources, time, and has the highest risk of a design – the verification effort. The SATA VIP has a Genie-SATA™ verification engine that wraps around the “Design Under Test” (DUT) to provide a complete framework to quickly develop self-checking, comprehensive tests for SATA-based Host and Target.