Adveda is a company in the domain of functional simulation and verification of software and hardware. Adveda helps both SW- and HW- developers to close the SoC verification gap by offering fast and fully integrated simulation and debugging tools.
The HDL Navigator is a dedicated HDL browser, which uses both the source code and the compiled result. For each signal the
origin(s) and destination(s) can easily be traced in the browser.
It provides full visibility, including current values of parameters and uses different icons to indicate wires, flip-flops, blocking assign, ...
SL2 (System Level Specification Language)
is an abstract descriptive language, developed to
generate fast cycle true simulation models of processor
cores and peripherals, suitable for multi-core firmware
development environments. As the potential of the
language is more versatile, it is extending to a
complete SoC modelling and specification language.
Univers COVER is the development tool for creating and verifying systems which include one or more CPU's and HDL designs.
Univers ISSIM is a multi-processor development environment. The Univers ISSIM IDE enables you to develop, build, debug and simulate CPU and/or DSP applications. Applications are project-based and can be comprised of C and/or assembler source files. Besides this, you can attach C++ peripherals.
Univers RTSIM is the stand-alone RTL Simulator. The RTL simulator is also part of Univers COVER. It is a blazingly fast digital simulator with a cycle-based kernel using 2-state logic models or 4-state logic models, resulting in simulations which are factors faster when compared with traditional simulators.