Adveda B.V.

Adveda is a company in the domain of functional simulation and verification of software and hardware. Adveda helps both SW- and HW- developers to close the SoC verification gap by offering fast and fully integrated simulation and debugging tools.


Product Name: HDL Navigator
Product Category: HDL Add-In Tools - ASIC and IC Design

The HDL Navigator is a dedicated HDL browser, which uses both the source code and the compiled result. For each signal the
origin(s) and destination(s) can easily be traced in the browser.
It provides full visibility, including current values of parameters and uses different icons to indicate wires, flip-flops, blocking assign, ...

Product Name: SL2 (System Level Specification Language)
Product Category: HW/SW Co-Debug - System Level Design (ESL)

SL2 (System Level Specification Language) is an abstract descriptive language, developed to generate fast cycle true simulation models of processor cores and peripherals, suitable for multi-core firmware development environments. As the potential of the language is more versatile, it is extending to a complete SoC modelling and specification language.

Product Name: Univers COVER
Product Category: HW/SW Co-Verfication - System Level Design (ESL)

Univers COVER is the development tool for creating and verifying systems which include one or more CPU's and HDL designs.

Product Name: Univers ISSIM
Product Category: DSP Design Tools - DSP

Univers ISSIM is a multi-processor development environment. The Univers ISSIM IDE enables you to develop, build, debug and simulate CPU and/or DSP applications. Applications are project-based and can be comprised of C and/or assembler  source files. Besides this, you can attach C++ peripherals.

Product Name: Univers RTSIM
Product Category: HDL Add-In Tools - ASIC and IC Design

Univers RTSIM is the stand-alone RTL Simulator. The RTL simulator is also part of Univers COVER. It is a blazingly fast digital simulator with a cycle-based kernel using 2-state logic models or 4-state logic models, resulting in simulations which are factors faster when compared with traditional simulators.  

Finistèrelaan 18
TD Eindhoven 5627
Phone: +31-40-2912385
Fax: +31-40-2912385
Contact us


Downstream : Solutuions for Post processing PCB Designs

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Senior Electrical Engineer for Allen & Shariff Corporation at Pittsburgh, Pennsylvania
Upcoming Events
Methodics User Group Meeting at Maxim Integrated 160 Rio Robles San Jose CA - Jun 5 - 6, 2018
2018 FLEX Korea at Room 402/ 403, COEX Seoul Korea (South) - Jun 20 - 21, 2018
IEEE 5G World FOrum at 5101 Great America Parkway Santa Clara CA - Jul 9 - 11, 2018
SEMICON West 2018 at Moscone Center San Francisco CA - Jul 10 - 12, 2018
DownStream: Solutions for Post Processing PCB Designs
Verific: SystemVerilog & VHDL Parsers
TrueCircuits: UltraPLL

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