Altos Design Automation Inc. (Acquired by Cadence)
Altos is an EDA company that provides ultra fast characterization technology to address key nanometer challenges such as low power, yield and process variation.
Altos Design Automation provides ultra-fast, fully automated, characterization technology for the creation of library views for timing, signal integrity and power analysis and optimization. Altos advanced modeling solutions are used by both corner-based and statistical-based design implementation flows to reduce time to market and improve yield.
Product Name: Liberate
- ASIC and IC Design
Liberate is an ultra-fast standard cell and I/O library creator. It generates electrical cell views for timing, power and signal integrity including advanced current source models (CCS and ECSM). It uses a unique “inside view” approach where each cell undergoes a pre-characterization circuit analysis that determines all the necessary stimulus and internal logic states to ensure a complete, accurate and highly efficient characterization of that cell.
Liberate LV provides a collection of utilities for validating libraries including functional equivalence checking, data consistency checking, revision analysis and correlation with various electrical analysis tools for timing (including statistical timing), noise and power. Using Liberate LV a complete validation of a library can be completed overnight on a small number of multi-core computers. For library providers, this assures the library quality before the library is shipped.
Liberate MX extends Altos’ ultra-fast standard cell and I/O library characterization capabilities to cover larger macro blocks such as memory, mixed signal and custom digital cores. Macro blocks require additional pre-analysis steps in order to make fast and accurate characterization feasible. Leveraging a network of distributed CPUs and utilizing Altos’ unique “inside view” technology for optimizing characterization runtime, memories and cores can be characterized quickly and easily with the same accuracy and methods as standard cells, including the generation of timing constraints and modeling of current source models for timing and noise.
Variety is an ultra-fast standard cell characterizer of
process variation aware timing models. It generates libraries that can be used
with multiple statistical timing analyzers without requiring
re-characterization for each unique format. It supports both linear and
non-linear sensitivity accounting for systematic and random variation for any
set of correlated or uncorrelated process parameters.