ICScape Inc.

ICScape Inc is an EDA software and low power IP provider. ICScape Inc provides innovative timing closure solutions for complex SOC designs. Focused on the back-end stage of IC designs, ICScape products provide designers more accurate, more easy-to-use, and more comprehensive design analysis utilities. Innovative vertical optimization products provide high quality of result (QOR) and significantly reduce the design closure time.

Product Name: ClockExplorer
Product Category: Design for Test - ASIC and IC Design

ClockExplorer is a comprehensive clock design environment which has major features: ClockAnalyzer is for clock structure analysis and constraint generation. Its functionalities include clock schematic creation, structure analysis, constraint verification, clock constraint generation, and design constraint merging.

Product Name: DBExplorer
Product Category: Documentation Tools - ASIC and IC Design

DBExplorer is a physical design database management and data analysis platform. It hyper-links design data that it is only click to do cross probing among data domains of layout, netlist hierarchy, gate level Verilog, SDC, connectivity schematic, and clock schematics.

Product Name: ICExplorer
Product Category: Design for Test - ASIC and IC Design

ICExplorer is the desired design analysis and optimization platform. Its analysis is accurate and its optimization is vertical thus it provides high QOR

Product Name: RCExplorer
Product Category: Design for Test - ASIC and IC Design

RCExplorer is a parasitic Extraction tool for Early-Stage and Post-Layout Simulation.Timing, signal integrity and power are becoming more challenging in multi-million gate designs, especially at 130nm node and below. RCExplorer can be a cell-level extraction tool for nanometer-scale standard cell designs. RCExplorer can also be transistor-level extraction with interface to 3rd part LVS tool, like Calibre.

Product Name: Skipper
Product Category: Layout Generators - ASIC and IC Design

Skipper is a powerful and extremely fast chip-finishing layout platform for ultra large scale chip designs. It combines an optimized database and highly effective memory management. It can handle huge designs with 100GB GDS data and performs fast data import, management, editing and searching operations with relatively small system resources, greatly reducing update time

Product Name: Timing Explorer
Product Category: Documentation Tools - ASIC and IC Design

TimingExplorer enables designers to diagnose their timing problems and provides fix solutions. The following are the list of major features of TimingExplorer:  Browse and analyze MCMM design timing reports. Narrow down the timing violation cause. TimingExplorer can be used as a pure timing report analyzer, which is also called TimingExplorer Lite.

2150 Trade Zone Blvd, Suite 107
San Jose, CA 95131
United States
Phone: 408-263-3900
Fax: 408-263-3907
Contact us
Url: http://www.icscape.com/
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MAPPS 2018 Summer Conference at The Belmond Charleston Place Charleston SC - Jul 22 - 25, 2018
International Test Conference India 2018 at Bangalore India - Jul 22 - 24, 2018
SRTC-2018 at The Leela Ambience Gurugram NEW DELHI India - Jul 25 - 26, 2018
MPSoC Forum 2018 at The Cliff Lodge 9320 South Cliff Lodge Drive Snowbird UT - Jul 29 - 3, 2018

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