Mirabilis Design provides systems engineering solutions for performance analysis, power estimation and architecture exploration of electronics and real-time software. Founded in 2003, Mirabilis Design is a privately funded technology company with offices in Sunnyvale, CA, USA and Chennai, India. Mirabilis Design has been growing at average annual rate of 250% and has been profitable since 2005. Mirabilis Design products merge the product development space between customer requirements, product development, marketing and customer support. Mirabilis products are used by architects and system engineers to explore the requirements and validate the specification prior to scheduling development
VisualSim Architect is the modeling and simulation desktop application from Mirabilis Design. The product is targeted at system engineers, architects, performance analysts and program managers. It is a full functionality package for Model-Based Design, Transaction Level Modeling and Cycle-Accurate modeling.Designers and architects can conduct trade-off studies by varying parameter values, executing different input traffic stimulus and modifying the system configuration including the topology.
he DSP and communications library provides basic DSP
functions and standard communications functions. The Communications Library provides Convolution
Encoders, Viterbi and Hammard
coding for the physical layer of communication systems.
VisualSim Explorer is a web Server that enables models to be embedded in documents and html pages for specification sharing and communication. The software is installed within the users's firewall or DMZ, depending on the required access rights. The product comes fully configured. To use the feature, the user adds a small script to the document. This script references the name of the model and the location of VisualSim Explorer.
VisualSim Processor and Peripheral Modeling Toolkit enables users to create processor models for performance anlysis and architecture exploration. Current generation Instruction Set Simulators offer very little visibility into the processor internals- a huge requirements for both Processor Architects and software designers.
VisualSim SmartMachine is a custom block authoring language, for quick prototyping of software instructions, algorithms and resource processing. The advantages are ease-of-learning, quick deployment, native code speed simulation performance, small code footprint and language flexibility.
VisualSim Xilinx FPGA Modeling Toolkit provides a virtual prototyping environment for performance analysis, architecture exploration and power optimization. This Modeling Toolkit works on the VisualSim Architect modeling and simulation environment. VisualSim Architect is a comprehensive environment for engineers to conduct performance, power and architecture exploration on the proposed system using a set of parameterized modeling components in a graphical block diagram editor.