iCODING Technology Incorporated
iCODING designs and produces high speed, high performance semiconductor products that incorporate turbo code decoders. These semiconductors can be used in a wide variety of communication applications, to improve throughput and range of transmissions.
The next wave of digital communication is broadband. iCODING brings the advantages of iterative coding technology, aka turbo codes, to this next wave. Turbo codes are a relatively new class of forward error correction codes that were introduced in 1993, by France Telecom. Error correction is one of the fundamental building blocks of all types of digital communications. Forward Error Correction (FEC) adds a redundant piece of information into the transmission which is then used to correct errors introduced during the transmission. The advantage of doing this is that noisy channels which would have been disregarded can be recovered, it also saves the time and power of re-transmitting the original signal.
The iCODING S3000 Turbo Decoder implements the standard 3GPPTM universal mobile telecommunications system (UMTS), rate 1/3, 8- state PCCC turbo decoder. It uses a highly efficient architecture to minimise area and memory usage whilst still providing the high performance through the use of a full log MAP implementation, combined with good internal parameter scaling/quantisation. This is all at a data throughput of up to 7 Mbit/s in FPGA. Handset throughputs of 2Mbit/sec are achieved with clock rates as low as 19 MHz.
The iCODING S4000 High Speed FPGA Turbo Decoder provides leading technology turbo code performance at exceptional data throughputs. Using the highly parallelizeable iCODING decoding core as a basis, the S4000 can achieve speeds in a single FPGA which were previously only possible in ASIC. Designed for both VirtexTM-E and VirtexTM –II Xilinx series of FPGAs, a wide range of speed/performance tradeoffs can be achieved, dependent on the selection of FPGA size and maximum block size.
The S7000 Turbo Code decoder core is a high speed decoder capable of decoding the 16 state parallel concatenated convolutional Turbo Code specified by the second-generation DVB-RCS2 standard. The decoder uses multiple parallel MAP decoders to process 4-8 bits per clock cycle with a minimum amount of overhead per iteration.