Automotive Integrated Electronics Corporation
AIEC was founded in 1992 with the goal of assisting automotive manufacturers in building better systems by helping them harness the power of custom silicon solutions. More than a decade and millions of vehicles later, we are proud to say that both we and our customers are achieving our goals.
We help our customers achieve success by working closely with them throughout the system definition and design phase. Being fully independent, we can offer our customers their choice among the most successful automotive semiconductor vendors in the industry, enabling them to have multiple-sourced solutions which ensures the lowest pricing and greatest continuity of supply.
The AIEC / ARM966E-S™ Microprocessor Core (AIEC9) is a high-performance, low-cost 32-bit microprocessor core that is intended as a platform for custom automotive System on Chip (SoC) developments. The high-performance of the AIEC9 is in part due to the memory architecture, which has been optimized for real time control systems where deterministic performance is achieved through execution of instructions directly from flash. An interleaved flash controller allows zero wait state execution of sequential code even with comparatively slow flash.
The AIEC9 System on Chip (SoC) Development Board (AIEC9DVB) provides an environment for developing production intent, custom SoCs that are based on the AIEC9 microprocessor (mP) core. Typically, an SoC contains a mP core, associated memory, digital peripherals, and an analog to digital converter. The AIEC9DVB provides provisions for all of these functions such that the SoC can be completely prototyped before committing to silicon.
The AIEC9 System on Chip (SoC) Development Board (AIEC9DVB) provides an environment for
developing production intent, custom SoCs that are based on the AIEC9 microprocessor (mP) core.
Typically, an SoC contains a mP core, associated memory, digital peripherals, and an analog to digital converter. The AIEC9DVB provides provisions for all of these functions such that the SoC can be completely prototyped before committing to silicon. In this way, a custom SoC can be developed to meet the requirements of a specific application while optimizing the system for performance and cost.
The ARM Processor Interrupt Controller (APIC) prioritizes and submits interrupt requests to the
microprocessor for servicing. The APIC is compatible with ARM7TDMI and ARM9TDMI microprocessor cores and allows expansion of ARM’s two interrupt sources to thirty-two interrupt sources with extremely low software overhead. One interrupt source can be routed to the ARM’s nFIRQ line for an extremely low latency interrupt source. Each interrupt source can be configured as a software or hardware interrupt.
The Real Time Engine Controller (RTEC) is an intelligent peripheral that is used in conjunction with a microprocessor for the control of internal combustion engines. RTEC has been specifically designed to increase engine performance and reduce emission output through precise delivery of ignition and injection pulses. RTEC’s advanced design features significantly reduce the servicing of interrupts by the controlling microprocessor, which effectively increases throughput allowing more complex control algorithms. The intelligent hardware contained within RTEC simplifies software development with the removal of many low-level routines normally required to control less intelligent peripherals.
The J1850VM fully supports the SAE Recommended Standard J1850 Class B Data Communication Network Interface for both single byte and consolidated headers using Variable Pulse Width (VPW) modulated bit encoding.
The J1850VM automatically handles the protocol details including message buffering, arbitration, frame delimiters, error detection, and cyclical redundancy generation and checking.
The Non-Intrusive RAM Overlay Calibration (NIROC) macrocell is designed to provide a real-time calibration solution for ARM9 microprocessor cores. Automotive powertrain applications involve large amounts of data which are used to define the operating parameters of the engine. These data are stored in “calibration tables” in instruction space. The values to be programmed into these tables are chosen during calibration. Traditional approaches to calibration have used parallel memory emulation technology.
The Serial Communications Interface (SCI) is an asynchronous full duplex serial communication
interface that uses standard Non-Return to Zero (NRZ) data formatting. The data format includes a single start bit, either 8 or 9 data bits, and a single stop bit. The last data bit can be programmed as either an odd or even parity bit. When enabled, parity is automatically generated by the transmitter and checked by the receiver. Parity errors detected by the receiver are indicated with the parity error flag.