MoSys, Inc. is a fabless semiconductor company enabling leading equipment manufacturers in the networking and communications markets to support the continual increase in Internet users, data and services.
MoSys® Bandwidth Engine® Family of ICs is a memory solution with serial interfaces and intelligent offload for high performance networking equipment. Bandwidth Engine is optimized for memory transaction performance, capable of up to 4.5 billion transactions per second, up to 400 Gbps effective data t throughput, and up to 12 billion operations per second when utilizing the counting and metering fixed macro operations.
The device architecture relies on three elements:
- A 576Mb multi-banked and multi-partitioned memory array built with high density 1T-SRAM® memory core and delivering the highest single chip transaction rate of any memory device in production today.
- Onboard ALUs for the acceleration of common statistics and metering functions for networking applications.
- Sixteen lanes of low latency SerDes, compatible with CEI-11G, supporting full duplex, concurrent operations with a packetized, 90% efficient GigaChip® Interface transport protocol.
The GigaChip® Interface is a reliable serial chip-to-chip transport protocol that operates over Optical Internetworking Forum (OIF) standard CEI SerDes and achieves 90% efficiency. The protocol, called the GigaChip Interface (GCI), can be scaled to 1, 2, 4 or 8 SerDes lanes as well as multiples of 8s. It targets computational and memory solutions with serial interfaces for networking equipment such as MoSys’ Bandwidth Engine® family of ICs. Operating on existing devices with 16 lanes at 15 Gbps, GCI provides enough bandwidth to support 4.5B read/write transactions and sufficient bandwidth to buffer full duplex 200GE. Doubling the pins or doubling the line rate (30Gbps) achieves full duplex 400GE.
The GigaChip Interface is groundbreaking technology that has been developed specifically for serial chip-to-chip communications targeting high-speed networking applications. Founded in July 2010 by MoSys, Inc., GigaChip Interface promoters include leading companies Altera Corporation, LSI Corporation , MoSys, Inc., and Xilinx, Inc.
MoSys® LineSpeed™ 100G PHYs are optimized to enable higher-density, lower-power data path connectivity as electrical interface rates transition from 10Gbps to 25Gbps, which is necessary to support 100G optical links. When combined with the packet processing offload capabilities of the Bandwidth Engine family of ICs, MoSys' solutions are enabling speed, density and intelligence in the network.