The current software development team, which still includes the architects of the initial LayTOOLS products, grew up in an era and location where software development was innovative and an art form. For them, in former East Germany, access to advanced tools was limited and communication with the rest of the world was restricted . Despite these handicaps, a software company was born, conceived by entrepreneurs fueled with imagination and driven by a futuristic vision which exploded after German Unification.

Product Name: LayED
Product Category: Design Verification

LayED is a powerful all-angles graphics editor especially developed for the layout of complex integrated circuits, including analog, digital, and mixed-signal designs.

Product Name: LayPAR
Product Category: Analog & Mixed Signal Simulators - ASIC and IC Design

The LayTOOLS Place and Route package (LayPAR) may be used as a stand-alone tool or as an integrated component of the LayTOOLS Suite. Although initially targeted at medium-sized designs (more than 100,000 gates) for mixed-signal application, it does integrate advanced algorithms which allow it to handle even larger numbers of cells and macros in an efficient manner without manual intervention.

Product Name: LaySIM
Product Category: Design Verification

One piece of software that an IC development software suite cannot do without is a simulator. With present day technologies, however, there are certain characteristics that are vital for such a tool. It must fully support the latest model formats, it should allow composite analog and digital net-lists to run ('gates' and transistors in the same net-list), it should converge reliably, and it should be able to provide straightforward approaches to analyses of such aspects as jitter and power consumption.

Product Name: LayVER
Product Category: Design Verification

LayVER is a sophisticated and comprehensive layout verification package that provides a complete set of tools to validate IC designs of any size and complexity. It offers database layer operations, provides spacing, intersection, extension, and sizing checks, as well as device and node extraction, with net-list comparison all under the same umbrella. With these features, design rule checks (drc), layout to schematic comparison (lvs) and parameter extraction (lpe) can be efficiently performed.

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