Magillem Design Services was incorporated in 2006, the robustness and maturity of the software have allowed for immediate growth through a build out of direct sales by Magillem Design Services to top-tier clients generating revenue and cash flow since the very first weeks.
Magillem has established partnerships with EDA vendors, universities and top European ESL R&D consortiums.
To accelerate the design of complex systems, such as System-on-Chip (SoC), and FPGA based solutions, the IP-XACT standard provides a mechanism for describing and handling multi-sourced IP that enables automated design integration and configuration within multi-vendor tool flows. To achieve these goals, Magillem presents MPA, the center piece of a powerful intuitive Integrated Design Environment.
The Master and Slave AMBA AHB bus wrappers are used to connect bus independent Intellectual Properties (IPs) to an AMBA AHB bus controller. They let system designers seamlessly integrate OCP compliant IPs in their system core, enabling a practical reuse methodology.
Magillem Generator Studio is a user-friendly and powerful environment to help designers implement, launch and debug their own executables (“generators”) in order to extend the capabilities of their IP based design environment.
Moving efficiently to an IP based methodology and flow requires legacy IP libraries to be captured in a technology independent format with an easy-to-use, scalable and automated process. Magillem IP Packager automatically creates an IP-XACT certified description for any VHDL, Verilog or SystemC component using a non-intrusive technology to your existing flow.
The Master and Slave AMBA AHB bus wrappers are used to connect bus independent Intellectual Properties (IPs) to an AMBA AHB
bus controller. They let system designers seamlessly integrate VCI compliant IPs in their system core, enabling a practical reuse methodology.
Two versions of the wrapper are available, one for masters and another for slaves. They both manage burst transfers in order to increase the bus throughput.
The Memory controller is used to interface a SDR memory to an AHB, OCP or BVCI host system core, which doesn’t have an internal SDR controller. Several subsystems (N) can share the same controller. Each bus channel can be configured separately with asynchronous clocks management. This controller includes an AMBA APB port for configuration management.