HDL design House


HDL Design House creates reusable IP cores, verification components and VITAL/VHDL models that meet the demanding requirements of your complex SoC (system-on-chip) and ASIC designs. We specialize in building dedicated engineering teams to deliver complete design and verification services to leading semiconductor companies. Our expertise in SoC design and verification as well as in SoC integration combined with HDL Design House products (IP cores and verification products) will provide our customers with a complete solution for SoC projects.




Product Name: JESD204B PCS IP Core
Product Category: Design Verification

The JESD204B Physical Coding Sublayer (PCS) IP Core enables both transmission and reception of data via a configurable number of Lanes to the SerDes interface, while guaranteeing data alignment and frame synchronization. The IP Core is responsible for frame generation, encoding, and scrambling for data transmission, as well as decoding, frame recovery, lane alignment and descrambling on data reception. HIP 600 is fully compatible with the JEDEC JESD204B specification.

Product Name: JESD204B PCS Rx IP Core
Product Category: Intellectual Property (IP) - ASIC and IC Design

The JESD204B RX Physical Coding Sublayer IP Core (HIP610) enables the reception of data via a configurable number of lanes from a Deserializer interface, while guaranteeing data alignment and frame synchronization. The HIP610 IP Core performs 8b/10b decoding, frame recovery, lane alignment, descrambling, and data demapping functions. In addition, it contains a set of test features, necessary to validate the data integrity on the serial interface. The HIP610 IP Core supports configurable number of DAC ports, each one having a width of up to 32 bits. The HIP610 IP Core offers the possibility to modify the behavior of the design based on the application requirements. This is done through the use of the design parameters, as well as via the Configuration Interface by programming the configuration registers.

Product Name: UVC/UVM VIP
Product Category: Verification - Structured/Platform ASICs

The Verification IP (VIP) for the Tensilica Processor Interface (PIF)® provides a quick and efficient way to verify PIF based SoC designs by implementing advanced techniques for more productive verification.PIF eVC is the complete solution for the verification of PIFbased systems. It has a complete built-in set of predefined coverage items and protocol checkers that are fully compliant with PIF protocol.


Golsvortijeva 35
Belgrade 11 000
Serbia
Phone: +381-11-414-5555
Contact us
Url: http://www.hdl-dh.com
Aldec

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Upcoming Events
IPC Technical Education - PCB Layout - Place and Route at Del Mar Fairgrounds 2260 Jimmy Durante Blvd. Del Mar CA - May 2, 2018
IPC Technical Education at Wisconsin Center 400 W Wisconsin Ave. Milwaukee WI - May 8, 2018
IPC High Reliability Forum at Embassy Suites: Baltimore-At BWI Airport 1300 Concourse Drive Linthicum MD - May 15 - 17, 2018
DownStream: Solutions for Post Processing PCB Designs
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