ASIC and IC Design : Formal Verification
Company: Atrenta, Inc.
SpyGlass-CDC is the industry’s most comprehensive, practical, and powerful Clock Domain Crossing solution. Spyglass-CDC automatically identifies and formally verifies all synchronization schemes that you throw at it.
Company: Atrenta, Inc.
Specify Constraints Early, Validate Continuously & Automate HandoffCreating and ensuring correct and consistent constraints, at all levels of the design hierarchy and throughout the design cycle, is a vital and increasingly challenging task. The difficulties can include: writing new constraints; managing thousands of lines of legacy constraints; managing thousands of timing exceptions across the design flow; unwanted iterations due to changing constraints; and erroneous constraints resulting in redesigns and even re-spins. The SpyGlass® Constraints solution provides a big productivity boost to IC design efforts by automating the creation, validation and management of constraints. The SpyGlass Constraints solution generates new constraints where needed and verifies that existing constraints are correct and consistent across all phases of development: pre-synthesis, pre-layout and post-layout.
AFS Nano Block-Level SPICE
Company: Berkeley Design Automation, Inc.
AFS Nano™ is the industry’s fastest SPICE simulator for
block-level IC design. Part of the AFS Platform, AFS Nano delivers
foundry-certified nanometer SPICE accuracy, 5x-10x faster for blocks with up to
5K elements. A one-year time-based license costs only $1,900 US.
Company: TEMENTO Systems
The Platform Edition includes all features of the Leading Edge Edition plus the Assertion Checker module. This IP allows the designer to embed his system assertions conditions written along with his system specifications before synthesis and check them at speed.
Company: Vector Cantech, Inc.
For testing and validating FlexRay systems there is a need forgreater precision in studying a system’ s behavior in response toerrors and disturbances. FRstress generates reproducible disturbanceson a channel in the FlexRay cluster. It can generate protocolerrors as well as disturbances in bus physics that are activated by trigger conditions. This gives the developer and tester a highperformance stress module.