ASIC and IC Design : Timing Analysis
Encounter® Timing System
Company: Cadence Design Systems, Inc.
Encounter Timing System serves both front-end logic designers
looking for high-quality timing analysis and ease of use, as well as
back-end implementation engineers requiring electrical analysis and a
common timing engine for silicon-accurate signoff.
Amber Path FX
Company: CLK Design Automation
Amber Path FX, with 40nm libraries from TSMC, is an accurate, fast, and
practical solution for high accuracy timing of nanometer designs. Amber
Path FX uses transistor level statistical static timing analysis (TSSTA)
to achieve near SPICE accuracy for both delay and variance.
At 65 nm and beyond, IC process variations present an increasing challenge to reducing design time while maintaining high yield. The CAT EDA software tool is used to achieve timing robustness in large-scale ASIC and System-on-Chip (SoC) designs.