Matches: 7
ASIC and IC Design : Layout Generators

Product Name: Skipper
Company: ICScape Inc.

Skipper is a powerful and extremely fast chip-finishing layout platform for ultra large scale chip designs. It combines an optimized database and highly effective memory management. It can handle huge designs with 100GB GDS data and performs fast data import, management, editing and searching operations with relatively small system resources, greatly reducing update time

Product Name: Ensigma RPU
Company: Imagination Technologies Ltd.

Ensigma™ Radio Processing Units (RPU) implement all of the connectivity and broadcast reception requirements of tomorrow’s complex SoCs. With more than thirty different deployable standards available for Ensigma RPUs today, they are the world’s most comprehensive baseband solution for integration into SoCs and advanced chipsets.

Product Name: Advanced Logic 65/55nm, 45/40nm
Company: SMIC

SMIC is the first foundry in mainland China to offer 40nm technology. SMIC offers its 40nm Low Leakage (LL) process with three threshold voltage core devices and 1.8V, 2.5V I/O options to meet various design application requirements. The 40nm logic process combines the most advanced immersion lithography, strain engineering technique, ultra shallow junction and ultra low-k dielectric for maximum power and performance optimization.

Product Name: Terminal
Company: Sontheim Industrie Elektronik GmbH

How do you conduct field bus analysis in different separated networks? Is there a way of having one single device handling all necessary diagnostics that can be carried around by service technicians if necessary – much like a PDA? Modern automation requires both high performance hardware combined with flexibility and durability in daily usage. Sontheim Industrie Elektronik GmbH has developed a highly mobile tool for exactly achieving these tasks. Mobi-CAN is a small industrial PC that has been designed for diagnostics in 11-Bit or 29-Bit identifier CAN-Bus networks.

Product Name: 3D ACIS Modeling
Company: Spatial Corporation

The 3D ACIS® Modeler (ACIS) is Spatial’s prominent modeling component used in over 350 customer applications with more than 2 million seats worldwide. ACIS features an open, object-oriented C++ architecture that enables robust, 3D modeling capabilities. It is particularly well-suited for developing applications with hybrid modeling features, since it integrates wireframe, surface, and solid modeling functionality with both manifold and non-manifold topology, and a rich set of geometric operations. ACIS provides a sound base of 3D modeling functionality, plus the flexibility to meet individual application requirements. The 3D solid modeler also includes ACIS extensions for specific application needs including hidden line removal, deformable modeling, advanced covering and defeaturing.

Product Name: HiPer DevGen
Company: Tanner EDA

HiPer DevGen accelerates the traditional analog layout process, saving time and increasing productivity, unlike the traditional “full custom approach” or new analog layout automation tools.  HiPer DevGen provides high performance device generation through analog layout acceleration that applies matching techniques to address common processing artifacts and produces the optimal solution for parasitics and silicon area in creating devices optimized for high yield.  HiPer DevGen can easily be applied to your standard methodology and flow; HiPer DevGen integrates with existing tools with no change in methodology, and can be easily setup in 20 minutes or less. FEATURES & BENEFITS:
  • Automatically generates common structures and primitives: Differential pairs, current mirrors, resistor dividers, MOS transistors, resistors and other basic structures.
  • Checks processing artifacts: Linear process gradients mask misalignment, implant shadowing, photolithographic invariance, current flow direction, mechanical stress/STI/LOD, antenna effect/Vt shift, WPE and more.
  • Supports general MOSET arrays and resistor arrays
  • Applies matching techniques to address common processing artifacts, parasitic and silicon area.
  • Uses manufacturing (DFM) design rules plus, DRC and LVS clean
  • Use any netlist through SDL in L-Edit
  • Works with unmodified schematics
  • Easy to setup and use; easy to use GUI with no CAD development required

Company: Tela Innovations

Tela power optimization software performs a comprehensive power and timing optimization of a finished design just prior to the handoff to manufacturing. No changes to any of the design layers are made during this optimization. Instead, the software outputs an annotation layer in the handoff GDSII database that gives detailed guidance to the OPC flow used in manufacturing.

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